Charles E. Stroud's A Designer’s Guide to Built-In Self-Test PDF

By Charles E. Stroud

ISBN-10: 0306475049

ISBN-13: 9780306475047

ISBN-10: 1402070500

ISBN-13: 9781402070501

A contemporary technological boost is the paintings of designing circuits to check themselves, known as a integrated Self-Test (BIST). this concept used to be first proposed round 1980 and has grown to turn into some of the most very important trying out options on the present time, in addition to for the longer term. This ebook is written from a designer's point of view and describes the foremost BIST methods which have been proposed and carried out due to the fact that 1980, besides their merits and barriers. The BIST methods comprise the integrated common sense Block Observer, pseudo-exhaustive BIST recommendations, round BIST, scan-based BIST, BIST for normal constructions, BIST for FPGAs and CPLDs, mixed-signal BIST, and the mixing of BIST with concurrent fault detection suggestions for online trying out. specific realization is paid to system-level use of BIST to be able to maximize some great benefits of BIST via lowered trying out time and price in addition to excessive diagnostic solution. the writer spent 15 years as a clothier at Bell Labs the place he designed over 20 creation VLSI units and three construction circuit forums. 16 of the VLSI units contained BIST of varied forms for normal constructions and basic sequential good judgment, together with the 1st BIST for Random entry stories (RAMs), the 1st thoroughly self-testing built-in circuit, and the 1st BIST for mixed-signal structures at Bell Labs. He has spent the prior 10 years in academia the place his learn and improvement keeps to target BIST, together with the 1st BIST for FPGAs and CPLDs in addition to persisted paintings within the sector of BIST for normal sequential common sense and mixed-signal structures. He holds 10 US patents (with five extra pending) for numerous varieties of BIST ways. hence, the writer brings a different combination of data and adventure to this functional consultant for designers, attempt engineers, product engineers, procedure diagnosticians, and managers.

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Fault Models and Detection requires special consideration during fault collapsing. The faults at the fan-out stem are not equivalent to the faults at the fan-out branches without violating the single stuck-at fault model assumption that there can be only one fault in the circuit. For example, the stuck-at-1 fault at the fan-out stem would be equivalent to a stuck-at-1 at the input to the NOR gate and a stuck-at-1 at the input to the NAND gate, violating the single fault model. Therefore, both the stuck-at-0 and stuck-at-1 faults at a fan-out stem must be included in the fault list (similar to a primary output).

Testing and Fault Simulation fault-free circuit simulation. If a mismatch is obtained for any test vector, the faulty circuit has produced an erroneous response compared to the fault-free circuit and the fault (or set of faults) is considered to be detected. As soon as a fault is detected, most fault simulators will stop simulating that fault (this is often referred to as fault dropping) and restart simulation at the beginning of the set of test vectors with the next fault in the list being emulated.

Obtaining the “warm, fuzzy feeling” that sufficient design verification has been obtained is a difficult step for the designer. While the ultimate determination is whether or not the design works in the system, fault simulation can provide a rough quantitative measure of the level of design verification much earlier in the design process. Fault simulation also provides valuable information on portions of the design that need further design verification (as we shall discuss shortly). The design verification vectors are often used as functional vectors during manufacturing testing.

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A Designer’s Guide to Built-In Self-Test by Charles E. Stroud


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